Fault Model and Test Synthesis for RISC-Processors

A general fault model on alternative graphs (AG) was developed to cover traditional functional and gate-level fault models for digital systems. The advantage of the new approach is that a uniform fault activating procedures on AG-s are applicable for different types of traditional faults. Also, it is not needed to represent functional faults explicitly by fault lists, the faults can be derived implicitly from the system description given by AGs. A hierarchical AG-based ATPG for a restricted class of digital systems (for RISC-processor type systems) was developed to carry out experiments for showing the adequacy of the AG-based fault model used in this ATPG against the gate-level stuck-at